opular RISC-V based MYTH workshop is back Despite...
# general
opular RISC-V based MYTH workshop is back Despite of having so many free resources on RISC-V microarchitecture design courses around the globe, VSD is proud to say that customers found our paid RISC-V based MYTH (microprocessor for you in thirty hours) 5-day workshop as the most structured one which hand-holds anyone and everyone who wants to learn RISC-V ISA and RISC-V uarch design from scratch. We had examples of 12/13-yr old students taking this workshop. Making workshops or courses free is more challenging as now you would have many eyes viewing your content, and one glitch in delivery might impact your brand. That's the reason, VSD free content and workshops are even more carefully curated. RISC-V based MYTH workshop last day for registration - 29th November, 11:59pm IST, 2021 Workshop dates - 1st - 5th December, 2021 (FYI - There are other Sky130 related workshops in same dates) Registration link - https://www.vlsisystemdesign.com/riscv-based-myth/ Mode of delivery - Workshop is on cloud. So you can login at your convenient time within 5-days, finish lectures/labs for the day and logout Workshop Day wise Content : Day 1 : Introduction to RISC-V ISA and GNU compiler toolchain 1. Introduction to RISC-V basic keywords 2. Labwork for RISC-V software toolchain 3. Integer number representation 4. Signed and unsigned arithmetic operations Day 2: Introduction to ABI and basic verification flow 1. Application Binary interface (ABI) 2. Lab work using ABI function calls 3. Basic verification flow using iverilog Day 3: Digital Logic with TL-Verilog and Makerchip 1. Combinational logic in TL-Verilog using Makerchip 2. Sequential and pipelined logic 3. Validity 4. Hierarchy Day 4: Basic RISC-V CPU micro-architecture 1. Microarchitecture and testbench for a simple RISC-V CPU 2. Fetch, decode, and execute logic 3. RISC-V control logic Day 5: Complete Pipelined RISC-V CPU micro-architecture/store 1. Pipelining the CPU 2. Load and store instructions and memory 3. Completing the RISC-V CPU 4. Wrap-up and future opportunities All the best and happy learning