https://open-source-silicon.dev logo
Channels
aa
abcc
activity
adiabatonauts
analog-design
announce
announcements
b2aws
b2aws-tutorial
bag
basebands
beagleboard
bluetooth
board-respin
cadence-genus
cadence-innovus
cadence-spectre
cadence-virtuoso
caravan
caravel
caravel-board
chilechipmakers
chip-yard
chipignite
chipignite2206q_stanford_bringup
chisel
coalition-for-digital-environmental-sustainability
community_denmark_dtu
containers
courses
design-review
design-services
dffram
digital-design
digital-electronics-learners
discord-mods
dynamic-power-estimation
efabless
electric
events
fasoc
fault
foss-asic-tools
fossee-iitb-esim
fossee-iitb-google-sky130
fpga
funding
fuserisc
general
generative-ai-silicon-challenge
genius-vlsi
gf180
gf180mcu
hardware-beginners
help-
ieee-sscs-cac-23
ieee-sscs-dc-21q3
ieee-sscs-dc-22
ieee-sscs-dc-23
ihp-sg13g2
images
infiniband
j-core
japan-region
junk
klayout
latam_vlsi
layouteditor
lvs
lvs-analysis
magic
magical
maker-projects
maker-zone
microwatt
mpw-2-silicon
mpw-one-clean-short
mpw-one-silicon
neuro-mem
nydesign
open_pdks
open-pdk
openadiabaticlogic
openfpga
openhighqualityresonators
openlane
openlane_cloudrunner
openlane-development
openocd
openpositarithmetic
openpower
openram
openroad
opentitan
osu
pa-test-chip
paracells
pd-openlane-and-sky130
picosoc
pll
popy_neel
power
private-shuttle
rad-lab-silicon
radio
rdircd
reram
researchers
rf-mmw-design
rios
riscv
sdram
serdes
shuttle
shuttle-precheck
shuttle-status
silicon-photonics
silicon-validation
silicon-validation-private
sky130
sky130-ci
sky130-pv-workshop
sky65
sky90
skywater
sram
stdcelllib
strive
swerv
system-verilog-learners
tapeout-job
tapeout-pakistan
team-awesome
timing-closure
toysram
travis-ci
uvm-learners
vendor-synopsys
venn
verification-be
verification-fe
verilog-learners
vh2v
vhdl
vhdl-learners
vliw
vlsi_verilog_using_opensource_eda
vlsi_verilog_using_opensoure_eda
vlsi-learners-group
vlsi101
waveform-viewers
xls
xschem
xyce
zettascale
Powered by
Title
k

Kunal

01/17/2022, 2:48 PM
Tapeout Program completes with STA workshop after 11 years It takes time to build anything great. We did run into obstacles, but quality of perseverance overcomes almost everything Building content for the "Tapeout Program" for the global semiconductor community really needed a good team of passionate industry leaders who are not only experts in their domain, but also share a similar vision. It is easy to find STA engineers, but (and this "but" comes with capital "B") it's really challenging to find STA leaders. Though I had enough experience doing STA in my previous jobs from device physics point of view, VSD needed to be fair with the community for such an important topic and decided to look for trusted partners.     VSD got lucky once again to have met Vikas Sachdeva - VLSI coach, trainer, Innovator, Speaker, Bachelor's from IIT Delhi and moreover an amazing human being. He got 8 publications and 2 patents under his belt. Vikas runs a very popular website "*vlsideepdive*" where he is an advisor for early stage products, courses, driving innovation in edtech, learning methods, professional training and coaching VSD is really glad to announce the next workshop with Vikas on "*Sign-off Timing Analysis - Basics to Advanced*" from 2nd to 6th Feb, 2022. The Indian government is pushing hard to propel innovation, build domestic capacities to ensure hardware sovereignty, and build a Semiconductor ecosystem that requires 85,000+ highly trained engineers. This engagement with Vikas is just the beginning of a long term relationship and we plan to work together deeply on Next gen VLSI EdTech which would cater to the needs of Indian semiconductor ecosystem Take a look at "Workshop Content" in below link. All the best and happy learning https://www.vlsisystemdesign.com/sign-off-timing-analysis-basics-to-advanced/