2 unique programs catering to next-generation VLSI...
# general
2 unique programs catering to next-generation VLSI recruits Program 1 – VSD-HDP (10-weeks from Jan 29 onwards) Link to register - ONFI Compliant NAND flash controller (Project code : ONFI) What is a NAND flash controller? Basically, when you have storage media like USB sticks or SSDs, they consist of interfaces like USB, NAND flash controllers and an actual flash, which stores the actual data. So, the NAND flash controller is responsible for the interface between your computer and actual flash storage chips. NAND flash controllers can have different interfaces, so they can interface with 1/8/16 flash chips. Even in SD cards, you have small controller inside it, and it’s interconnected with the flash inside SD cards So, flash controllers are needed in all kinds of storage devices Now what does the flash controller look like? What are they doing? For example, typical flash controller consists of CPU, it has some RAM/ROM, it has a DMA engine which is responsible for transferring data, then there is a NAND flash controller which optionally has ECC for error correction of the flash, its connected to actual flash chip, usually outside of the controller The flash controller uses the ONFI flash protocol which is an effort for standardizing the communication protocol between NAND flash controller and actual flash Let’s take a deeper look into the flash controller – it reads and writes content from small RAM, it has control registers, it has ECC for error correction and NAND flash interface then talks to NAND flash memories which are usually separate IP requirements: ·       ONFI compliant minimum 3.1 ·       An ECC core is optional, we could do that in software ·       Minimum 1 flash channel, optionally up to 16 channels, preferably configurable ·       Language: Verilog 2005 or TL-Verilog ·       Target Platforms o  FPGA ICE140 – IceStick/IcoBoard o  ASIC – Skywater 130nm PDKs Program 2 – VSD-IAT (5-days from Feb 2 onwards) Link to register - Sign-off Static Timing Analysis – Basics to Advanced Really glad to conduct a 5-day lab intensive Sign-off Timing Analysis workshop with Vikas Sachdeva . It really needs an open-mindedness to adapt to a more effective form of cloud lab-based learning. Open-minded participants who have completed similar workshops in the past are doing very well in industry as it needs utmost sincerity, smart-work and hard-work to complete a 5-day workshop with a lab score of above 80%. This format brings the best out of your technical and managerial abilities, which is a very important skill needed by industry Times have changed, and the industry is looking for candidates who are open to all kinds of challenges presented to them. So, all the best, give your best and notice the change for yourself All the best and happy learning