Last 6 hours to close STA workshop registration https://www.vlsisystemdesign.com/sign-off-timing-analysis-basics-to-advanced/ A great chance to create cool STA Project repository showcasing your STA skills to whole world. Workshop content (Lectures and Labs) Day1 Lectures 1. STA Definition 1. Timing Paths 1. Timing path elements 1. Setup & Hold Checks 1. Slack Calculation 1. SDC Overview 1. Clocks 1. Generated Clocks 1. Boundary Constraints Day1 Labs · OpenSTA Introduction · Understanding basics of OpenSTA · Inputs to OpenSTA · Constraints creation · OpenSTA Run script Day2 Lectures 1. Other timing checks 1. Design Rule Checks 1. Latch Timing 1. STA Text Report Day2 Labs · Liberty Files and Understanding Lib Parsing · Understanding SPEF file and SPEF parsing · Understanding OpenTimer tool messages · Understanding timing reports and timing graphs Day3 Lectures 1. Multiple Clocks 1. Timing arcs and Timing Sense 1. Cell Delays and Clock Network 1. Setup and Hold Detailed 1. STA Text Report Day3 Labs · Understanding full reg to reg STA analysis · Understanding Slack computation · Understanding and reviewing setup check report Day4 Lectures 1. Crosstalk and Noise 1. Operating modes and other variations 1. Clock Gating Checks 1. Checks on Async Pins Day4 Labs · Understanding clock gating check · Understanding Async pin checks Day5 Lectures 1. Clock groups 1. Clock properties 1. Timing exceptions 1. Multiple modes Day5 Labs · Revisit slack computation · Understand CRPR · ECO insertion