Last 14hrs to get all my online VSD-VLSI courses for $5/$9 or Rs.360/Rs.700 each based on your location Sharing Tips again Tips on order in which you need to learn VLSI and become a CHAMPION (especially for students/freshers): If I would had been you, I would had started with Physical Design course where I understand the entire flow first, then would have moved to CTS-1 and CTS-2 to look into details of how the clock is been built. Then, as you all know how crosstalk impacts functioning at lower nodes, I would gone for Signal Integrity course to understand impacts of scaling and fix them. Once I do that, I would want to know how to analyze performance of my design and I would have gone for STA-1, STA-2 and Timing ECO webinar courses, respectively Once you STA, there’s an internal curiosity which rises, and wants us to understand, what goes inside timing analysis at transistor level. To full-fill that, I would had taken Circuit design and SPICE simulations Part 1 and Part 2 courses. And finally, to understand pre-placed cells, IP’s and STA in even more detail, I would have taken custom layout course and Library Characterization course All of above needs to be implemented using a CAD tool and needs to be done faster, for which I would have written TCL or perl scripts. So for that, I would start to learn TCL-Part1 and TCL-Part2 courses, at very beginning or in middle Now once my fundamentals are cleared and if I want to learn RTL and synthesis, from specifications to layout with a example design, I will go in below order (Only after I finish all above courses): 1. RISC-V ISA course Part 1a and Part 1b will teach the best way to define specs for a complex system like microprocessor 2. Then I will go for RISC-V Pipeline RTL design 3. Next would go for RISC-V SoC Design which involves SoC planning and integration 4. Finally I would go for RISC-V physical design and Layout All VLSI courses using FPGAs and Skywater 130nm PDKs done by VSD-HDP Interns are below (Use these for your next tapeout) VSD – Mixed signal RISC-V based SoC on FPGA https://www.udemy.com/course/vsd-mixed-signal-risc-v-based-soc-on-fpga/?couponCode=B7660FE44C49D51D509E VSD Intern – Mixed Signal Physical Design flow with OpenLANE/Sky130 https://www.udemy.com/course/vsd-intern-mixed-signal-physical-design-flow/?couponCode=5B03AA9D084922BDBD34 VSD Intern – OpenRAM configuration for 4kB SRAM using Sky130 https://www.udemy.com/course/vsd-intern-openram-configuration-for-4kb-sram-using-sky130/?couponCode=DFF67B18521CC9F5FBA4 VSD Intern – Analog Bandgap Reference design usingSky130 https://www.udemy.com/course/vsd-intern-analog-bandgap-reference-design-using-sky130/?couponCode=831B0E2FD347A3AABC16 VSD Intern – Analog comparator design usingSky130 https://www.udemy.com/course/vsd-intern-analog-comparator-design-using-sky130/?couponCode=F2BC16263B87BB3B555A VSD Intern - DAC IP design using Sky130 PDKs - Part 1 (specifications) https://www.udemy.com/course/vsd-intern-dac-ip-design-using-sky130-pdks-part-1/?couponCode=0558063C3ECDEF3EC36F VSD Intern - DAC IP design using Sky130 PDKs - Part 2 (circuit design) https://www.udemy.com/course/vsd-intern-dac-ip-design-using-sky130-pdks-part-2/?couponCode=6764CDF3D0886B26D163 VSD Intern - DAC IP design using Sky130 PDKs - Part 3 (layout) https://www.udemy.com/course/vsd-intern-dac-ip-design-using-sky130-pdks-part-3/?couponCode=3AB4AD87B6DCA411EC09 VSD Intern – 10-bit DAC design using eSim and Sky130 https://www.udemy.com/course/vsd-intern-10-bit-dac-design-using-esim-and-sky130/?couponCode=C76E17176C948FAC744A Connect with me for more guidance !! Hope you enjoy the session best of luck for future