Upcoming OSFPGA workshop FAQs There have been many queries by you about content which we are planning to cover in the upcoming "RISC-V on FPGA" workshop organized by the OSFPGA foundation. Let me answer this query with the above image. If you observe, once you receive and develop your specs, there are two branches - FPGA flow and ASIC flow. Generally, it's a good idea to fully test your design on FPGA before going for ASIC as ASIC flow is huge time-to-market. In the upcoming RISC-V on FPGA workshop, the specs which we will be covering is RISC-V ISA, and that is Course 1). We will be quickly testing and verifying the RISC-V core (which you developed in Course 1) by integrating it with an on-board PLL using Xilinx Zedboard and that is Course 2). Finally, we will understand the entire FPGA flow, build our FPGA and test the same RISC-V core (which you developed in Course 1) on the FPGA fabric which you learn in Course 3). If you want to understand RISC-V and its implementation from the basics (like a newbie), a suggestion would be to take Course 2) and Course 3) jointly with Course 1), The below link covers curriculum details about all courses (limited number of students) https://osfpga.org/osfpga-training/ All the best and happy learning