RISC-V workshop starting soon Did you know the best part of learning computer architecture? You can build a basic CPU using muxes, which you have learnt as a part of digital logic design. On top of that, TL-Verilog makes it simple to pipeline your CPU and convert your outcome into standard IEEE format Verilog netlist in a few seconds which is FPGA proved and Silicon ready Thanks to Open-Source FPGA Foundation, for the first time, you are receiving a $70 workshop at just $30, which is more than 55% discounted from the original price. It's limited to the top 100 participants and registration closes on 24hrs Here's the link for registration https://pages.razorpay.com/osfpga-riscv All the best and happy learning