efabless sponsored Physical Design workshop content
If there's one image which captures the content of the upcoming
efabless sponsored "Physical Design workshop using Skywater 130nm PDK", it's the one shown below. Before any sponsorship discussion, VSD and efabless make sure of the fact that the content should cater to participants who have little to no clue about chip design but eventually should be able to tapeout using SKY130. And all of this in a high-intensity, lab-based 5-day workshop format. Here's the link with registration details
https://www.vlsisystemdesign.com/advanced-physical-design-using-openlane-sky130/
Thanks to efabless sponsorship, for the first time,
VSD can provide more than a 55% discount on this workshop. Take a look at the below content
Day 1 Inception of Open Source EDA
Skywater PDK Files
Invoking OpenLANE
Package Importing
Design Folder
Design Folder Hierarchy
Configuration Files
Prepare Design
Synthesis
Day 2 - Floorplanning and Standard Cells
Aspect Ratio and Utilization Factor
Preplaced Cells
Decoupling Capacitors
Power Planning
Pin Placement
Floorplanning with OpenLANE
Viewing Floorplan in Magic
Placement
Viewing Placement in Magic
Standard Cell Design Flow
Standard Cell Characterization
Day 3 - Design Library Cell
Spice Simulations
Switching Threshold of a CMOS Inverter
16 Mask CMOS Process Steps
Magic Layout View of Inverter Standard Cell
Magic Key Features
Device Inference
DRC Errors
PEX Extraction with Magic
Spice Wrapper for Simulation
Day 4 Layout Timing Analysis and CTS
An Introduction to LEF Files
Standard Cell Pin Placement
LEF Generation in Magic
Including Custom Cells in OpenLANE
Fixing Slack Violations
Clock Tree Synthesis
Viewing Post-CTS Netlist
Post-CTS STA Analysis
Day 5 Final Steps in RTL to GDSII
Power Distribution Network Generation
Global and Detailed Routing
SPEF Extraction
All the best and happy learning