anyone interested in system-level verification of an open FPGA design? I think it'd be interesting to set up a simulation harness where you can program a bitstream over jtag or w/e, have the design interface with virtual peripherals like uart, spi, i2c (maybe MII, ULPI, etc in future generations), and do some DFT type stuff (boundary scan/atpg if supported, and some way to inspect/dump LUT FF state kinda like an open source chipscope if the architecture supports that)