@User I have not thought about this idea. OpenFPGA support WE + DIN pins for the memory cells inside LUT, so that partial reconfiguration can be done at runtime. But the WE + DIN pins are controlled by the configuration protocol only, rather than datapath logics. The major concern why the memory cells are not driven by datapath signals (again this is my personal opinion) is the writing speed for these memory cells are slower than datapath logics. It means your critical path delay will be bounded by the LUT configuration.