Join Slack
Powered by
Hello, I'm trying to run the generated verilog by ...
# openfpga
b
Baloch
04/14/2021, 5:59 AM
Hello, I'm trying to run the generated verilog by OpenFPGA through the OpenLANE flow but it is failing synthesis because of multiple drivers, has someone tried this or knows how to resolve this?
3
Views
Open in Slack
Previous
Next