@User This is actually not a problem from yosys. This is due to that you are the technology mapped netlist from OpenFPGA, which is not synthesizable. The use of technology mapped netlist is to drive the place & route of OpenROAD directly. Or you can try our synthesizable netlists at https://github.com/lnis-uofu/OpenFPGA/tree/master/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/synthesizable_verilog/config