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<@U0169AQ41L6> Yes. We changed the default_net_typ...
# openfpga
x
Xifan Tang
05/07/2021, 10:06 PM
@User
Yes. We changed the default_net_type to wire and hacked some verilog netlists. This works. Also we have try the openPDK, which process the Verilog netlists in a similar principle as our hacking. It also works.
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