Normally a pipelined design has a certain maximum delay between each stage, measured in the number of circuit levels with a typical fan out of four (FO4 - https://en.wikipedia.org/wiki/FO4). You can have more pipeline stages with less delay or fewer stages with more delay. Obviously if your cell library has a cell that has a delay of 3 FO4 all by itself then any design that uses it can't have pipeline stages with a lower delay than that