Hi , Maybe is a basic problem but unfortunately I am not experienced with RTL . I want to connect the wishbone from caravel chip to an SRAM , but I have some issue (functional): • for gpio example I see that the registers are written/read with the condition

stb_i, cyc_i , we_i and ack_o

signals • I implemented similar variant and somehow the internal sram, data_in gets values that are skipped by one clock. • also

ack_o

is toggling although I expect not to • source,test bench and wave forms code can be found here: https://github.com/MihaiHMO/VSDhdp/tree/main/Spice Maybe somebody can give me a feedback what am I doing wrong. Thanks.