Mihai Hurdugaciu02/17/2023, 8:59 AM
signals • I implemented similar variant and somehow the internal sram, data_in gets values that are skipped by one clock. • also
stb_i, cyc_i , we_i and ack_o
is toggling although I expect not to • source,test bench and wave forms code can be found here: https://github.com/MihaiHMO/VSDhdp/tree/main/Spice Maybe somebody can give me a feedback what am I doing wrong. Thanks.