Has anyone tested any of the OpenRAM macros on MPW2 yet? I have some `sram_1rw1r_32_256_8_sky130` th...

gatecat

02/13/2023, 4:09 PM

Has anyone tested any of the OpenRAM macros on MPW2 yet? I have some

sram_1rw1r_32_256_8_sky130

that on a very brief test aren't responding (but I certainly can't rule out a problem in my test setup or integration at this point, so don't treat it as a writeoff).

gatecat

02/13/2023, 5:12 PM

ah, actually, I'm curious, does OpenRAM have a minimum clock? I see some life out of it when running at 10MHz, whereas at 1kHz (ish) I just get zeros out

gatecat

02/13/2023, 5:19 PM

ahhh, pebcak... I missed that the data is invalid between the posedge and negedge. checking read data at the negedge now it works fine at 1kHz too

Matthew Guthaus

02/13/2023, 5:35 PM

We are still doing bring-up on our test chip. We tested essentially that same macro pre-MPW and it was working up to ~12MHz.

Matthew Guthaus

02/13/2023, 5:36 PM

(It was limited by IO delays)

👍 2

Matthew Guthaus

02/13/2023, 5:36 PM

Yes, data should become valid some time after the negative edge. The first half of the cycle is precharge and then read occurs in the second half.

Matthew Guthaus

02/13/2023, 5:40 PM

Actually, that macro is the exact one we tested in silicon. Not the updated one.

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