<https://ieeexplore.ieee.org/document/9937426>
# generalj
James Stine
02/13/2023, 2:17 PMa
Art Scott
02/13/2023, 2:22 PMWhat effort required to tapeout at efabless? Is there a Verilog or VHDL file? TTD 2023 get some posit to efabless chip.
James Stine
02/13/2023, 2:17 PMArt Scott
02/13/2023, 2:22 PM