I am currently trying to get the UART running on MPW2 chips, but whatever I tried, it didn't work. Now I would like to be able to analyze how the uart_tx signal is actually generated. I would like to have a tool that is able to analze a signal/net (e.g. uart_tx) and tells me where that signal gets generated in caravel, where it is connected to, similar to the net-tracing feature of PCB design software where you can select a single pad or net, and then it can highlight all nets and pads it is connected to. I think in this case we might want a netlist that contains references to the original verilog sourcecode. I am not sure whether yosys can do that already, but I guess we might be able to enhance yosys to do it. And then a tool that lets you work through the netlist, and display the verilog sources on demand, this could be done in some kind of IDE (Eclipse, Visual Studio, or a web app ...). How do you do such an analysis? Just by using grep?

I agree with Philipp, having a net tracing tool that traverses the hierarchy of the design is extremely import. I am new to all the open-source cad tools and do not personally know of a tool that can do the net tracing. If someone knows of such a tool please point it out to the group.

Load the DEF/ODB file

openroad -gui

and use

Find

option for searching for the nets. More OpenROAD gui features found here: https://openroad-flow-scripts.readthedocs.io/en/latest/tutorials/FlowTutorial.html#openroad-gui

@Philipp Gühring In some examples I have generated a schematic from a verilog synthetized netlist. See this link. A counter has been translated from verilog to schematic and after some simple editing (like removing the filler cells and decaps) the resulting schematic has been simulated at the gate level with spice. However the process is not "push button", there is some work and editing to be done. If you have an example netlist I can test again this procedure I did a year ago... may be something has changed in the mean time. In xschem you can highlight any net and trace back to its generation for inspection. This whole process makes sense for medium to small circuits. Bigger systems need probably different and more automated debugging tools.