I have been trying to test out the Management UART and have written a small code for the same

void set_registers()
{

    reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
    reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT;
    
}

void main()
{
    reg_gpio_mode1 = 1;
    reg_gpio_mode0 = 0;
    reg_gpio_ien = 1;
    reg_gpio_oe = 1;

    set_registers();
    
    gpio_config_io();

    reg_gpio_out = 1; // OFF
    
    reg_uart_enable = 0xff;
    
    while (1)
    {
        
        reg_gpio_out = 0;
        delay(1000000);

        while (reg_uart_txfull == 1)
            ;
        reg_uart_data = 0x61;

        reg_gpio_out = 1;
        delay(1000000);
    }
}

on running this code both Tx and Rx remain pulled high on the logic analyser. Is there something that i am missing out? also is the configuration in

set_registers()

correct?

You have both registers 5 and 6 marked as outputs in

set_registers()

. GPIO[5] (Rx) should be set as

GPIO_MODE_MGMT_STD_INPUT_NOPULL

, or else the management SoC will try to drive that line instead of getting input from it (technically, the setting should be

MGMT

, not

USER

, although only one bit of the setting is used to determine which direction the GPIO is communicating, so only

INPUT

or

OUTPUT

matters). Maybe more importantly is to ask what is in your

gpio_config_io.py

file. Are you setting channel 5 to management input and channel 6 to management output?

Changed GPIO[5] to input in both

set_registers()

and

gpio_config_io.py

and also

MGMT

instead of

USER

. I still get the same results where both the lines are pulled high.

void set_registers()
{

    reg_mprj_io_5 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; //Rx
    reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;       //Tx
 
}

void main()
{
    reg_gpio_mode1 = 1;
    reg_gpio_mode0 = 0;
    reg_gpio_ien = 1;
    reg_gpio_oe = 1;

    set_registers();
    
    gpio_config_io();

    reg_gpio_out = 1; // OFF
    
    reg_uart_enable = 0xff;
 
    while (1)
    {
 
        reg_gpio_out = 0;
        delay(1000000);

        while (reg_uart_txfull == 1)
            ;
        reg_uart_data = 0x4f;

        reg_gpio_out = 1;
        delay(1000000);
    }
}

That's

C_MGMT_IN

and

C_MGMT_OUT

in

gpio_config_io.py

?

I also unsuccessfully tried getting the UART running in various ways, my test code is available at: https://github.com/thesourcerer8/mpw2-stdcell-tests/tree/main/uart_test If anyone can get it running, I would be happy about a report or a pull-request for necessary changes

The PicoRV32 implementation of the UART was blocking. I don't know about the VexRISC implementation, but I'm guessing that according to the code that you reference, it's non-blocking and has a FIFO buffer.

I found my bug, I have UART working! 🙂

Philipp, did you get TX and RX to work?

I only tested TX yet.

ok

another datapoint about UART, it seems that caravel pins

E7

and

F7

(respectively mapped to

mprj_io[5]

and

mprj_io[6]

) seems to be connected to

UART8

of the nucleo board, but I don't see it being defined in the micropython HAL: https://github.com/micropython/micropython/blob/05bb26010e4a466a82cfed179f8d8d0b406a78ca/ports/stm32/boards/NUCLEO_F746ZG/mpconfigboard.h#L32-L39