@jeffdi @Tim Edwards do we have a breakdown of the steps needed to solve https://github.com/efabless/caravel_user_project_analog/issues/40 ?

I can do the minimum of replacing 11 GPIO along the top and sides with analog pads. There will be fewer options, as we don't have IP for allowing analog connections to GPIO pads; they're digital only. I could do something like double up pads with an analog pad next to each digital pad, and wire bond (or bump bond) them together, but that would drastically change the characteristics of the digital pads.

Wouldn't

gf180mcu_fd_io__asig_5p0

work as an IP for analog pad?

Sorry, failed to answer your question. Sure, you can document the options in the issue. BTW, yesterday I started some verilog and layout for the caravan chip on GF; it's currently checked into the

caravel-gf180mcu

repository under branch

caravan_development

. Mainly I just cobbled together the analog padframe (just swaps out 11 GPIO pads for 11 analog pads), then generated the verilog for the padframe and top level. What I have not done is to define where the user analog project area is. It depends a bit on how much room the synthesis tools need around the sides.

oh that's awesome, I was mainly looking forward documenting what needs to be done in order to enable others to contribute but it's great to see progress!