I am getting LVS errors when trying to build sky130_sram_1rw_tiny right out of the box; sequence of commands is git clone -> cd into openram folder -> set env vars -> make pdk -> make install -> cd into macros -> make sky130_sram_1rw_tiny Am I doing something wrong? Both stable and dev branches give me the same result ...

@alex d Getting the openram macros to pass LVS with magic and netgen can be tricky because 1. some layout cells do not have bulk/well contacts 2. some layout cells have multiple unconnected power rails with the same text 3. netgen creates proxy pins for unmatched ports in otherwise matching circuits. This works if the ports are not connected, but may cause problems if the nets are merged at a higher hierarchy. There are work arounds for all of these issues. Can you post your gds and spice? I’ll take a look and may be able to suggest something.

Here you go, and just to clarify, this is right out of the box with no modifications made of any sort (fresh repo clone running the sky130_sram_1rw_tiny example through docker). If it was failing after I made some changes to it I would understand that I messed something up and it would be on me, but LVS issues right out of the box seems odd

@alex d I've found that it is very dependent on which version of Magic and netgen. There were many changes over a year or so that kept adding issues with the items @Mitch Bailey mentions. You are using the docker so that was the last known version to work for us.

So I'm not doing anything "wrong" per se, right?

No, nothing at all wrong.

I have never seen this magic warning before:

[openram.verify.magic/run_lvs]: Warning: Equate pins: cell sky130_fd_pr__special_pfet_pass is a placeholder, treated as a black box.

[openram.verify.magic/run_lvs]: Warning: Equate pins: cell sky130_fd_pr__special_pfet_pass is a placeholder, treated as a black box.

I believe all device models that are extracted as subcircuits have this message. It is not (generally) a problem.

(This has been my biggest frustration in the whole project, to be honest.)

I sort of chuckled when I read that. From the tool side, one of the biggest frustrations has been dealing with layout and schematics that only match at higher levels. Hopefully there’s some relatively simple solution.