Hello. I have a Question about the Synthesis in OpenLane. My Design has 2 inputs clk1 and clk2 . When I did synthesis on OpenLane. Synthesis gets fails every time. But this design works properly after synthesis using Cadence Genus. I have tried 2 possibilities in config file the screenshots are attached below. Anyone knows How to do synthesis using 2 input clocks in Openlane. This is my first post/message so errors may be expected.

how does it fail?

I am attaching the log files. What is the correct way to define 2 clocks in the config file?

I just see "Source not found." which doesn't sounds like has anything to do with clocks

meaning? No, the Synthesis every time Gives new errors. I do not understand why . One more thing, How I Should define 2 clocks of different frequencies, will you please write the correct formate of command I want to double sure about it.

@M_Naveed_Abbasi Can you share source RTL/config.json/constraint.sdc

The config file is attached

Its killed due to memory issue.

[ERROR]: during executing: "yosys -c /openlane/scripts/synth.tcl -l /openlane/designs/wrapper_top/runs/Synth_3/logs/synthesis/1-yosys.log |& tee >&@stdout"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child killed: kill signal

Increase your swap memory and run the flow again

Swap memory means?

check this: https://open-source-silicon.slack.com/archives/C016H8WJMBR/p1650317104192279?thread_ts=1650215768.620859&cid=C016H8WJMBR

Hi thanks for this slack. The issue is with the RAM I am not 100 % sure yet, But most like RAM issues. I need (width = 64 and Depth = 256 ) which is equal to 2KB memory size (I guess). I need four of them in my whole design. I am using window 10 as an OS, and Installed VM to use Openlane. I have 4 GB of RAM in total Installed in my Laptop and I have provided 2 GB RAM to openlane. I tried to use the max swap memory but I can go up to 16GB maximum in Windows 10. Synthesis got failed. (even for smaller memory size of width = 8 and Depth = 8 ) I am only synthesizing the memory module.

Your block is too small to fit the pins around the edge

Replace

RAM_256_64

into pre-built OpenRAM sram macro

pdks/sky130A/libs.ref/sky130_sram_macros/lib/sram_1rw1r_32_256_8_sky130*

or generate own from https://github.com/VLSIDA/OpenRAM here

Thanks for the Help. I was able to synthesize the memory module, by increasing the SWAP memory in VM. its looks like I need more RAM resources for my laptop. now after interfacing memory modules with my design, I am getting the same errors. Now I am going to do synthesis on another PC having higher resources. I need to arrange it. Will update you soon. Thanks again!