Does anyone have any idea what is wrong?

Stanley Lin

02/03/2023, 10:06 PM

Does anyone have any idea what is wrong?

Stefan Schippers

02/04/2023, 12:25 AM

I have tried to do the following: first of all i have set very high precision flags:

.option ABSTOL=1e-14 GMIN=1e-14 RELTOL=1e-5 VNTOL=1e-8

Then in the .control section i have run 2 DC simulations, one with

vip

going forward and one going backward:

dc vip 0 3.3 0.1

write op.raw

set appendwrite

dc vip 3.3 0 -0.1

write op.raw

simulation shows 2 different transfer characteristics. It looks like the DC value of

v(out)

is indeterminate, this happens for example if the output has no dc paths to ground or vsupply and any DC level is a valid solution. Check carefully your circuit. May be some transistors are in Off state and carrying pA of current. However i don't have the schematic, so i can not investigate further.

Stanley Lin

02/04/2023, 12:28 AM

Oh I see. Actually my output is a high impedance output stage of a general BJT op amp. I thought the output voltage could be determined by the two BJTs even though this is a high impedance node. Maybe in gf180 model, the vout couldn't be just determined by the BJT's operating point

Stanley Lin

02/04/2023, 12:29 AM

I will make some experiments, hopefully I can find out what happens to my circuit

Stefan Schippers

02/04/2023, 12:29 AM

you can add a high resistor from out to gnd, like 100MOhm. This will probably remove indetermination.

Stanley Lin

02/04/2023, 12:30 AM

Oh okay

Stanley Lin

02/04/2023, 12:30 AM

Thank you for your advice

Stefan Schippers

02/04/2023, 12:30 AM

ps: use 100MEG not 100M in spice (100M is 100 milliohm) !

Stefan Schippers

02/04/2023, 12:32 AM

the resistor doesn't seem to fix the issue....

Stefan Schippers

02/04/2023, 12:32 AM

can you attach the .sch file(s)?

Stanley Lin

02/04/2023, 12:32 AM

Yes

Stanley Lin

02/04/2023, 12:41 AM

BJTamp.sch

Stanley Lin

02/04/2023, 12:42 AM

btw what is the different between 100MEG and 100M? I thought both of them stand for 100*10e6

Stefan Schippers

02/04/2023, 12:56 AM

no, m stands for "milli", 1e-3. Since spice is case insesitive 1mF and 1MF both refer to 1 milli Farad

🌍 1

Stanley Lin

02/04/2023, 12:57 AM

Oh yeah I see

Stefan Schippers

02/04/2023, 12:59 AM

I found a serious issue in the design. You need to edit the npn symbol and change the name of the substrate pin to S, it is set to 'B'. This creates a substrate to base short.

Stefan Schippers

02/04/2023, 12:59 AM

this is not your fault this must be notified upstream

Stefan Schippers

02/04/2023, 1:00 AM

in the fg180 pdk maintainers

Stefan Schippers

02/04/2023, 1:00 AM

but the fix is easy. descend into the symbol, select the small red square , press 'q' and change name=B to name=S

🌍 1

Stefan Schippers

02/04/2023, 1:10 AM

I also don't know if the S node of the transistor must be connected to the emitter or to AVSS

Stanley Lin

02/04/2023, 1:12 AM

Actually I have changed the terminal from B to S before since the simulation will fail if that isn't changed

Stefan Schippers

02/04/2023, 1:14 AM

yes i have seen, however this change must be done. It is not changing the behavior though

Stanley Lin

02/04/2023, 1:15 AM

Yeah

Stefan Schippers

02/04/2023, 1:23 AM

I can't understand the biasing of the output stage. You have 2x1k resistors and 2 diodes. As a result Vbe of output bipolars is ~0.9V these transistors are in super ON state and you have 40mA flowing from AV33 to AVSS.

Stefan Schippers

02/04/2023, 1:23 AM

1.png

Stefan Schippers

02/04/2023, 1:26 AM

the diodes themselves are carrying 30mA of current. The differential stage can add/subtract some mA, but this is largely insufficient to drive the outputs.

Stefan Schippers

02/04/2023, 1:29 AM

If you want a push pull stage you must swap pnp and npn output transistors

Stanley Lin

02/04/2023, 1:30 AM

截圖 2023-02-03 下午8.30.03.png

Stanley Lin

02/04/2023, 1:30 AM

Actually I think you get the correct operating point which is consistent with dc simulation

Stanley Lin

02/04/2023, 1:30 AM

This is the result of my op simulation

Stefan Schippers

02/04/2023, 1:33 AM

I have changed the ouput stage to push pull and get abetter transfer function:

Stanley Lin

02/04/2023, 1:35 AM

Could you send me this .sch file?

Stanley Lin

02/04/2023, 1:35 AM

I'll spend sometime digging into it

Stanley Lin

02/04/2023, 1:36 AM

To be honest I am not quite familiar with the BJT design

Stefan Schippers

02/04/2023, 1:36 AM

yes i will send it. Anyway i still see mismatch between the op and dc sims... This is probably an issue with the BJT spice models, not with the simulator itself...

Stanley Lin

02/04/2023, 1:37 AM

However it seems that you didn't have that inconsistency issue in you previous screenshot

Stanley Lin

02/04/2023, 1:38 AM

image.png

Stanley Lin

02/04/2023, 1:38 AM

This one

Stanley Lin

02/04/2023, 1:38 AM

Is it under op simulation?

Stefan Schippers

02/04/2023, 1:47 AM

no image above was one dc point, dont' remember exactly what vip value... You can backannotate any point in a dc sim, it is explained in this video. The schematic with output transformed to push pull:

LT6200.sch

🌍 1

Stanley Lin

02/04/2023, 1:48 AM

Okay, thank you so much!

Stanley Lin

02/04/2023, 1:48 AM

This is very helpful

6 Views

Open in Slack

Previous Next

What is Linen?

Linen is a search-engine friendly community platform. We offer integrations with existing Slack/Discord communities and make those conversations Google-searchable.