apothem
02/03/2023, 9:00 PMMatt Liberty
02/04/2023, 4:36 AMapothem
02/04/2023, 6:52 PMMatt Liberty
02/04/2023, 9:08 PMapothem
02/05/2023, 3:05 AMMatt Liberty
02/05/2023, 3:06 AMapothem
02/05/2023, 3:08 AMMatt Liberty
02/05/2023, 3:09 AMapothem
02/05/2023, 5:49 PMVijayan Krishnan
02/06/2023, 5:32 AMapothem
02/06/2023, 10:44 AMVijayan Krishnan
02/06/2023, 10:44 AMiomem_rdata
port connection.apothem
02/06/2023, 10:45 AMVijayan Krishnan
02/06/2023, 10:46 AMapothem
02/06/2023, 10:47 AMVijayan Krishnan
02/06/2023, 10:52 AMIf the signal is completely hanging without connecting to anything else, we can remove it.
If it is completely undriven but is used for loading something else, like a flop, the RTL needs to be revisited and the logic has to be fixed. Any piece of logic cannot have an undriven input.
If it is a bus, which is partially driven and the bits that are not driven are inconsequential, as in, if they are not expected to drive anything else downstream, then it can be potentially waived off after review. The preference would still be to remove those bits that are not driven and are not used to load anything.
As a matter of practice, we do not use multi driven nets in design. It can also lead of unnecessary verification holes that can potentially cause a short.
As others have pointed out, unused nets and flops can get optimised in synthesis tools, but the right practice is to remove them in the RTL itself.
apothem
02/06/2023, 10:53 AMMatt Liberty
02/06/2023, 4:41 PMapothem
02/06/2023, 9:17 PMMatt Liberty
02/06/2023, 9:18 PMapothem
02/07/2023, 10:14 AM