Hi everyone. I'm creating an AC simulation for an analog cell I designed. Currently, it's just metal connecting the input (M5) to the output (M3). The AC output of the testbench circuit should resemble a low-pass filter response. However, after performing the RC extraction, the simulation results in a flat band response at all frequencies up to 100GHz. I suspect the problem may be related to the R extraction, but I'm not sure why. Does anyone have any ideas what could be causing this?. I used these commands for the RC extraction: extract do local extract all ext2sim labels on ext2sim extresist tolerance 10000 extresist ext2spice lvs ext2spice cthresh 0 ext2spice extresist on ext2spice quit

Take a look at the extracted netlist and you will have an answer. Not the solution, of course.

@Luis Henrique Rodovalho Yes, I looked at the netlist generated (3rd image). It seems that there are almost no parasitic resistances extracted. I don't know if it's due to a bad execution of the command, or if that's really how the extraction results should be.

First, make a op point simulations. A 1 V DC source and see the current.

Thanks a lot, @Luis Henrique Rodovalho! I remade the simulations with your recommendations and it worked! Now its behavior resembles a low-pass response. I'll create a pin for the substrate in the layout for an ideal way of extraction. Here, as you can see, it appears that the bandwidth of the cell is quite high. In your experience, would you say this is "normal" for a piece of metal?

Plot db(v(out)) next time. It is so small it is not the biggest problem. A diode at the ESD protection would have greater parasitic capacitance. use`.meas ac f0 when db(vout)=-3` to find the cutoff frequency