Hello there, I am trying to harden a RISC-V core with some peripherals and custom memory macros from OpenRAM but I don't really get if I can run the flow with all verilog files (including core, uart, spi, pwm, axi...) and expect it to arrange everything or should I harden the peripherals, memory controllers and core seperatly and combine them later. if is there any documentation about it, it wil be really helpful.