Hi guys, i am try to simulate this simple circuit. I am using the logic from pdk library. I don't understand this error. Any suggestion?

Can you share your spice file? I’m guessing the correct library is not being included.

** sch_path: /home/roberto/Documents/circuits/digital_logic/tb_phase_gen.sch **.subckt tb_phase_gen x1 VDD clk_in ph_1 ph_2 GND phase_gen V1 clk_in GND pulse(0 3.3 1n 1n 1n 498n 1u) .save i(v1) V2 VDD GND 3.3 .save i(v2) C1 ph_2 0 0.5p m=1 C2 ph_1 0 0.5p m=1 ** begin user architecture code .option savecurrents .control save all tran 0.01n 10u plot v(clk_in) v(ph_1) v(ph_2) .endc .lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt **.lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/all.spice tt ** end user architecture code **.ends * expanding symbol: /home/roberto/Documents/circuits/digital_logic/phase_gen.sym # of pins=5 ** sym_path: /home/roberto/Documents/circuits/digital_logic/phase_gen.sym ** sch_path: /home/roberto/Documents/circuits/digital_logic/phase_gen.sch .subckt phase_gen hsup clk_in ph_1 ph_2 lsup *.ipin clk_in *.opin ph_1 *.opin ph_2 *.iopin lsup *.iopin hsup XC1 net3 lsup sky130_fd_pr__cap_mim_m3_1 W=10 L=5 MF=1 m=1 XC2 net5 lsup sky130_fd_pr__cap_mim_m3_1 W=10 L=5 MF=1 m=1 x10 clk_in ph_2 lsup lsup hsup hsup net1 sky130_fd_sc_hd_nor2_1 x2 ph_1 net6 lsup lsup hsup hsup net7 sky130_fd_sc_hd_nor2_1 x1 net1 lsup lsup hsup hsup net2 sky130_fd_sc_hd__inv_2 x3 clk_in lsup lsup hsup hsup net6 sky130_fd_sc_hd__inv_2 x6 net5 lsup lsup hsup hsup ph_2 sky130_fd_sc_hd__inv_2 x5 net3 lsup lsup hsup hsup ph_1 sky130_fd_sc_hd__inv_2 x7 net2 lsup lsup hsup hsup net3 sky130_fd_sc_hd__inv_2 x8 net4 lsup lsup hsup hsup net5 sky130_fd_sc_hd__inv_2 x4 net7 lsup lsup hsup hsup net4 sky130_fd_sc_hd__inv_2 .ends .GLOBAL GND .GLOBAL VDD .end

Looks like

sky130.lib.spice

only includes the primitive devices. I was going to suggest including the standard cell spice too, but the spice symbols in your netlist are missing VPWR VPB VGND VNB ports.

.include /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice

Also looks like you’re trying to simulate with VDD=3.3V. The thin-ox devices in the standard cells are rated at 1.8V. @Stefan Schippers probably knows how to get the sky130A standard cell symbols to simulate in hgspice.

@Roberto Di Lorenzo Add this line in your simulation:

.include $::SKYWATER_STDCELLS/sky130_fd_sc_hd.spice

Or if you know the path:

.include /path/to/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice

this file contains all the spice netlists of the standard cells (inverters, nand gates, flops etc). Also, as @Mitch Bailey mentioned, select all logic cells together (by clicking with the shift key) then press 'q', check the 'Preserve unchanged props' checkbutton, and ensure to assign your VCC and VSS to the power/subbstrate attributes. The standard cell symbols don't have power pins but these are implicitly assigned as attributes. This makes the symbols look less cluttered with power pins (and you can change power connection of the whole logic with one single edit attribute operation!).

I renamed this connections. I used "hsup" and "lsup", this logic can works only at 1.8V? if i want to work with 3.3 i have to create all the stardard cell?

Maybe you can change all the prefixes to

sky130_fd_sc_hvl

at once.

for 3.3V you need HV standard cells, so you can try to select all standard cells, (click using Shift key) then press 'q' and change the prefix attribute to

sky130_fd_sc_hvl

, (remember to check

preserve unchanged props

to avoid changing other attributes). I have not made tests with hvl standard cells, so let us know if it works. Remember also to include the right spice netlist file for these standardcells:

.include /path/to/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice

I have a good news to share. This is working for me.