hello. I'm new to ASIC (I have done some tinkering with FPGAs though). my goal is to create an hdmi retimer for 1080p@60hz (dvi -> rgb -> dvi). is this remotely within the capabilities of the process? I was having a look at the docs for the io cell and it mentioned something about 33MHz https://skywater-pdk.readthedocs.io/en/main/contents/libraries/sky130_fd_io/docs/user_guide.html surely designs aren't limited to 33MHz?

Digital io cells are limited to 33 MHz output. You can go over that limit by using analog io. There were a few successful tapeouts in the 1-3 GHz range on previous shuttles, but all of them were analog designs.

11 bare pins +30+ mixed (digital + analog pins) You can connect to the mixed pads and drive them, but it cant get out of 0 - VDDIO because of ESD protection diodes AND you need to handle ESD protection yourself.

I mean, we were doing 1 GHz chip designs in 0.13/130nm 20+ years ago at IBM, so the tech can do it for sure - but with the caravel wrapper differential signaling is tough (impossible?) and you’d need to build the IOs yourself - which is not a trivial affair. Also, with the space restrictions you might have trouble. However, I do encourage you to give it the ol’ college try if you can get some people to help you with the design that are a bit more experienced.