Hi @Mitch Bailey , I have question on the LVS. How to blackbox specific circuit on lvs? I want to debug some issue, it will be helpful if I can do that. Thanks

There are (at least) 3 things you can do to prevent an error in a subcircuit from propagating all the way to the top of the design. The first is to use the

-noflatten=<filename>

option of

lvs

command in netgen.

lvs "gds.spice top" "verilog top" setup.tcl lvs.report -blackbox -json -noflatten=noflatten.list

The second method is to set the cell to be a LEF cell before extraction. If you’re extracting from gds, use something like this.

gds read <gdsFile>

load <black-box-cell> -dereference
property LEFview true

load <topcell> -dereference

The third thing you can try, is to remove the verilog/spice cell. That should cause an automatic black box comparison.

Thank you, I will try it