is there a guide on doing a full chip simulation for analog?

Generally, full-chip analog is not possible due to the number and complexity of components on the board. What you probably want to do is to make sure you have tested your analog circuit in isolation, and maybe with some I/O pad models. If your design is mixed-signal and interacts with the chip's processor, then you should create a simple verilog model for your circuit to test that the digital connections and signaling work as expected. If not, then LVS at the level of the user project wrapper should suffice. In principle, it should be possible to create an xspice model of the entire processor, but I'm not sure how well ngspice will cope with simulating the entire padframe. It is probably worth attempting.

How would I do a LVS with my current .sch file

See the example

caravel_use_project_analog

under the

xschem/

directory. This has a schematic and symbol for

user_analog_project_wrapper

, and includes a simulation testbench at the level of the wrapper. The wrapper netlist is used for LVS.