@Pranav Lulu After Nov.24th xschem and the xschem_sky130 symbols have been modified by adding a '`lvs_format`' attribute (in addition to
format
that sets the spice netlisting rule) that defines the netlisting rule if
Simulation->LVS netlist: top level is a subckt
is selected. In LVS mode the netlist for a mos transistor looks like:
XM1 net1 G1v8 S B sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 m=1
instead of:
XM1 net1 G1v8 S B sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
so area / perimeter params are not generated. The device line contains
L, W, nf and m
which should be enough for checking vs layout.
@Tim Edwards if netgen needs also area and perimeter for S/D regions let me know, if it does do i need to present the calculated values in the LVS netlist (or does netgen understand equations?)