I wrote. I hope it will help beginners. https://vlsi.jp/RgGenxOpenMPW_eng.html

Where can I find the list of community guides?

@Cra2yPierr0t awesome, maybe do a PR against OpenLane repo's README? (and post it to #openlane)

I liked the guide. but I have a small question, what does CSR mean?

CSR means *C*onfiguration and *S*tatus *R*egisters.

@Ilya Lapshin Community guide list is here! https://openlane.readthedocs.io/en/latest/additional_material.html#community

By using RgGen, you can generate RTL, UVM reg model, C header file and Markdown document from readable register map specifications such as Ruby, YAML and MS Excel. RgGen repository: https://github.com/rggen/rggen Sample: https://github.com/rggen/rggen-sample

@proppy Thanks! I just posted it!

@Cra2yPierr0t This looks pretty good! Lots of details. I am quite interested in the testing part at the end of your document. But, a dumb question: What is GL? I see this a lot in the templates and I have no idea.

@Rolf Widenfelt Thanks for the question, I guess GL refers to the one mentioned in the testbench section of the article. The files in

verilog/gl/

are all the files in

verilog/rtl/

that you use are compressed into one file, and It is used for simulation (and possibly for building layouts). It is automatically generated when

make <design_name>

is run, so the user only needs to add the path to the file in

verilog/include/

.

@Cra2yPierr0t Will do! Thank you!

@donn I've submitted a pull request! Thank you!

GL = gate level