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Hi , need to do a RTL to RTL - logical equivalence checking - which open source tool is best to use ?? ( if it exists !) Thanks in advance

Yosys does have support for adding equivalence cells and generating miter circuits from them. Then you can use its formal verification functionality. Here's an example: <https://stackoverflow.com/questions/47745223/reset-behavior-with-miter-equivalence-checking>

Well, next time, if you're going to ask in two different places and get an answer in one of them, post it to the other places (in this case, linking to your thread in <#C016H8WJMBR|openlane>)

What is Linen?