how can i resolve this issue

attach 21-rcx_sta_min.rpt

21-rcx_sta.min.rpt

attach logs/signoff/22-rcx_sta.log

21-rcx_sta.log

Update your

config.json

with

IO_PCT : 0.3,

and try

how to update it

you've worst slack of 23ns. Do you want to reduce clock period further?

no

{
  "DESIGN_NAME": "arbiter_puf",
  "DESIGN_IS_CORE": 0,
  "VERILOG_FILES": [
    "dir::../../verilog/rtl/defines.v",
    "dir::../../verilog/rtl/arbiter_puf.v"
  ],
  "CLOCK_PERIOD": 10,
  "CLOCK_PORT": "ipulse",
  "CLOCK_NET": "ipulse",
  "FP_SIZING": "absolute",
  "DIE_AREA": "0 0 200 200",
  "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
  "PL_BASIC_PLACEMENT": 0,
  "PL_TARGET_DENSITY": 0.55,
  "VDD_NETS": [
    "vccd1"
  ],
  "GND_NETS": [
    "vssd1"
  ],
  "DIODE_INSERTION_STRATEGY": 4,
  "RUN_CVC": 1,
  "pdk::sky130*": {
    "FP_CORE_UTIL": 45,
    "RT_MAX_LAYER": "met4",
    "scl::sky130_fd_sc_hd": {
      "CLOCK_PERIOD": 10
    },
    "scl::sky130_fd_sc_hdll": {
      "CLOCK_PERIOD": 10
    },
    "scl::sky130_fd_sc_hs": {
      "CLOCK_PERIOD": 8
    },
    "scl::sky130_fd_sc_ls": {
      "CLOCK_PERIOD": 10,
      "SYNTH_MAX_FANOUT": 5
    },
    "scl::sky130_fd_sc_ms": {
      "CLOCK_PERIOD": 10
    }
  },
  "pdk::gf180mcuC": {
    "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
    "CLOCK_PERIOD": 48,
    "FP_CORE_UTIL": 45,
    "RT_MAX_LAYER": "Metal4",
    "SYNTH_MAX_FANOUT": 4,
    "IO_PCT": 0.3,
    "PL_TARGET_DENSITY": 0.45
  }
}

Update your file like attached and try again

ok will do thanks

do you have git repo for this project?

i hav introduction to open MPW

"PL_RESIZER_HOLD_MAX_BUFFER_PERCENT": 80,
"PL_RESIZER_HOLD_SLACK_MARGIN": 0.8,
"GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT": 80,
"GLB_RESIZER_HOLD_SLACK_MARGIN": 0.8,

try to change above variable and see the timing report

@Vijayan Krishnan it is preferrable to open a GH issue rather than send me a problem in slack.

@Neha Maheshwari do you want to fix the hold violation?