Has anyone tried using the "logic analyzer" IOs that are part of the Caraval structure? It seems like an interesting thing to experiment with.

It's a pretty simple structure. In effect, it defines exactly what you might do yourself with a simple wishbone interface in the user project driving some registers for simple read and write operations on a handful of signal lines (bits), but it defines the wishbone interface part for you so you don't have to, and gives you 64 full-duplex signal lines to use.

The user_defines.v file sort of makes sense to me. I will look for an example though.. the last thing I'd want to mess up is connecting two outputs together :(

I have been using it for my standard cell test designs, since I was running out out IOs, so I attached the remaining cell IOs to the logic analyzer.

@Rolf Widenfelt: Anything done in

user_defines.v

can be undone or modified with a simple program running on the SoC.

@Tim Edwards good to know! hoping I get to that stage :)