I have used only 36 ports, but still it giving thi...
# general
r
I have used only 36 ports, but still it giving this error
v
child killed signal mostly related to memory problem. Can you share your repo link or rtl file?
r
v
what is your system RAM size?
k
16Gb
v
increase swap memory and run again. still running with peak memory of 14GB now
@rakshith Update your config.tcl following variables and run:
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set ::env(SYNTH_STRATEGY) "DELAY 4"
also comment
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#set ::env(FP_SIZING) absolute
#set ::env(DIE_AREA) "0 0 900 600"
Chip area for module '\bisection': 5149961.151998
r
Hello sir, sorry for the delayed response, We are trying to synthesize our project, but still we are getting the same error. How did you synthesize and get the area? You commented the statements in .tcl file and ran it?
v
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set ::env(SYNTH_STRATEGY) "DELAY 4"
use above synthesis strategy and try