How to solve this error?

It cant find the dlatch. Do you have one in your design?

I haven't used dlatch in my design

Perhaps your verilog is causing a dlatch to be inferred

@rakshith is that sky130 or gf180 pdk?

gf180

latch_map.v missing for gf180 pdk. For sky130 pdk latch_map.v as follows

module \$_DLATCH_P_ (input E, input D, output Q);
  sky130_fd_sc_hd__dlxtp_1 _TECHMAP_DLATCH_P (
    //# {{data|Data Signals}}
    .D(D),
    .Q(Q),

    //# {{clocks|Clocking}}
    .GATE(E)
  );
endmodule

module \$_DLATCH_N_ (input E, input D, output Q);
  sky130_fd_sc_hd__dlxtn_1 _TECHMAP_DLATCH_N (
    //# {{data|Data Signals}}
    .D(D),
    .Q(Q),

    //# {{clocks|Clocking}}
    .GATE_N(E)
  );
endmodule

file issue here: https://github.com/The-OpenROAD-Project/OpenLane/issues