lame question :
Is there any cmmd to have lib cells , nets and pins in the netlist on oneline in yosys write verilog ??
sky130_fd_sc_hd__and2_0 07 (
.A(In2),
.B(In1),
.X(03)
);
sky130_fd_sc_hd__and2_0 08 (
.A(Cin),
.B(03),
.X(04)
);
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