This is the spice model of a RAM .subckt gf180mcu_fd_ip_sram__sram512x8m8wm1 VSS CLK D[0] A[8] A[7] A[2] A[1] A[0] + Q[2] Q[3] CEN A[5] A[6] A[4] WEN[3] D[7] Q[7] D[3] D[1] D[2] A[3] Q[1] Q[6] D[5] + Q[4] WEN[5] WEN[2] WEN[1] WEN[4] WEN[7] WEN[6] D[4] D[6] Q[5] Q[0] GWEN WEN[0] Don't see a VDD pin. Is it fine?