Hi @Mitch Bailey, I am getting LVS error while running caravel_user project_wrapper. I can see "sky130_fd_sc_hd__conb_1 " has pin "HI" that is not present in verilog netlist but present in layout. it is also showing net mismatch issues. I did'nt get how to resolve this? @

A quick way to deal with this, especially if there is only one (or few) of the

conb_1

gates in the design, is to hand-edit the verilog and add the missing pin, as in:

sky130_fd_sc_hd__conb_1 inst (
    .HI(),
    .LO(signal),
    .VGND(VGND),
    .VNB(VGND),
    .VPB(VPWR),
    .VPWR(VPWR)
  );

Tools like yosys will leave the pin out instead of including it with a NULL connection (both methods are valid verilog syntax). You can also add a placeholder module definition for the cell, but that's a bit more complicated than just editing the netlist.

Okay. But it is having large numbers of sky130_fd_sc_hd__conb_1 . So what can be the other way to deal with it?

Actually, all you need to do is to edit the first occurrence.

@Tim Edwards why is that even an LVS error as a dangling pin makes no difference to the connectiviity?

@Deepak what version of netgen are you using?

@Matt Liberty: I forget the exact mechanism. I agree that it shouldn't be an error, and I have tried to address it several times. Ultimately, the problem arises from the fact that netgen was originally designed for SPICE netlists as was not coded with any expectation that pins might simply be omitted.

@Mitch Bailey I am using netgen 1.5.227 version

Could you try a more recent version?

okay let me update and check once

Take a look at the layout. It looks like openlane is trying to do synthesis at the top level and placing

conb

cells. However, I bet that these cells aren’t being placed in normal routed cell rows (no fill, decap or tap cells). What you probably want to do is tie all your low/high inputs in your

SRAM_Wrapper_top

instead of

user_project_wrapper

.

@Deepak Can you share your repo link or user_project_wrapper verilog file?

@Vijayan Krishnan Please find the attached user_project_wrapper verilog file

/*--------------------------------------*/
/* User project is instantiated  here   */
/*--------------------------------------*/
SRAM_Wrapper_top SRAM_IMC_TOP(
`ifdef USE_POWER_PINS
    .vccd1(vccd1),	// User area 1 1.8V power
     .vssd1(vssd1),	// User area 1 digital ground
     .VDD(vccd2),
     .VSS(vssd2),						//currently taking out to LA
`endif

.clk(wb_clk_i),					//Common clock
.reset_n(wb_rst_i),					//wb_rst_i	
.wbs_we_i(wbs_we_i) ,					//wbs_we_i=0 for read ;wbs_we_i=1 for write		
.wishbone_buffer_data_in(wbs_dat_i), 			//wbs_dat_i
.wishbone_rw_addr(wbs_adr_i),				//wishbone_addr
.VCLP(analog_io[11]),					// connect to Analog IO
.EN(analog_io[12]),					// connect to Analog IO
.Iref0(analog_io[7]),					// connect to Analog IO
.Iref1(analog_io[8]),					// connect to Analog IO
.Iref2(analog_io[9]),					// connect to Analog IO
.Iref3(analog_io[10]),					// connect to Analog IO
.wishbone_databus_out(wbs_dat_o),	 		//wbs_dat_o
.EN_VCLP(la_data_in[120])				//Deepak_28/11/22: needs to be passed to analog DUT for EN & VCLP enable
); 

endmodule	// user_project_wrapper

Can you try this format of power pin declaration?

okay, will try that "FP_PDN_MACRO_HOOKS": ["SRAM_IMC_TOP vccd1 vssd1 vccd1 vssd1","SRAM_IMC_TOP vccd2 vssd2 VDD VSS"], this way..right??

yes

Yes, I changed config & verilog file accordingly as per above and run" make user_project_wrapper". This also resulted with LVS error.

is same error or did you find change in log?

The error is same as ..sharing screenshot of log file.

have you tried Mitch Bailey suggestion to update macro rtl?

One more thing I have ran "SRAM_Wrapper_top" instance with openlane flow with similar assignment of power pinslike above...there i did not get this error. In user project wrapper , i just used that as macro.

yes

okay, I tried with this as well but getting same error.

share me your configuration file for the wrapper run

This is the configuration file for the same

Update following variables and try to power

conb_

standard cell:

"FP_PDN_ENABLE_RAILS": 1,
    "RUN_FILL_INSERTION": 1,
    "RUN_TAP_DECAP_INSERTION": 1,

@Deepak There have been reports about

FP_PDN_MACRO_HOOKS

. Try adding a comma between the second

vssd1

and the

"

"FP_PDN_MACRO_HOOKS": ["SRAM_IMC_TOP vccd1 vssd1 vccd1 vssd1,","SRAM_IMC_TOP vccd2 vssd2 VDD VSS"],

okay @Mitch Bailey, I tried options mentioned by @Vijayan Krishnan, LVS error got clear . Now after this on running MPW precheck locally it is getting stuck at "consistency check" -{{STEP UPDATE}} Executing Check 5 of 14: Consistency

Are you using the latest precheck repo?

Yeah latest one

When you say “getting stuck”, do you mean there’s an error, or that the execution time is long?

I mean execution time is long...it was taking long time....more than hour(so i exited from the run)

I don’t know, but I don’t think so.