Hi anyone tried to do a RTL test with gf180mcu? I was trying to launch a test with `make verify-la_t...
i
Hi anyone tried to do a RTL test with gf180mcu? I was trying to launch a test with
make verify-la_test1-rtl
and I got and error that
/dependencies/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/verilog/gf180mcu_fd_sc_mcu7t5v0_udp.v: No such file or directory
. Why the node is needed for a rtl test?
v
i
Yes,
# Caravel user project includes
-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
-v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v
-v $(USER_PROJECT_VERILOG)/ecc_registers/register_file.v
-v $(USER_PROJECT_VERILOG)/ecc_registers/register_data.v
-v $(USER_PROJECT_VERILOG)/ecc_registers/data_verificator.v
-v $(USER_PROJECT_VERILOG)/ecc_registers/decoder_output.v
-v $(USER_PROJECT_VERILOG)/ecc_registers/parity_calculator.v
-v $(USER_PROJECT_VERILOG)/ecc_registers/state_counters.v
I found this. In the folder that is searching, the name of the .v file is different of what is calling in the docker
image.png
dependencies/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/verilog/gf180mcu_fd_sc_mcu7t5v0_udp.v
I should change the name of that file?
v
Is testbench.v updated as per hardened macro?
i
in theory I'm launching and RTL test, is not harden yet
I just found this issue. That is exactly the same as me https://github.com/efabless/caravel_user_project/issues/212
m
AFAIK, simulation isn't well supported on GF180
t
The UDP primitives in the verilog were missing from the Google repository and just got added a few days ago. This makes gate-level simulation a "work in progress". We fixed a bunch of code around the gate-level verilog modules in the efabless fork of the Google repository, and I updated open_pdks to sort it all out. The current version (as of late yesterday) is very similar in structure to the sky130 version, but none of this has been tested yet as far as I know. That said, though, I'm not sure why an RTL test is throwing a gate-level error. Probably because there is an
include
statement that gets processed when the verilog library is read. The latest open_pdks removes all the
include
statements.
🌍 1
i
as I found, seems that is calling to two files, gf180mcu_fd_sc_mcu7t5v0_udp.v and gf180mcu_fd_sc_mcu7t5v0.v. Only the later is in the corret directory, and the other is not found in the PDK