I’ve found that hierarchical extract works best if there are pins defined at every level.
You can look at the extracted netlist and find subckts with ‘#’ in the port names - I suggest adding layout pins or flattening before extraction (no need to flatten the actual cells, just set the files to flatten before reading gds.)
@Mitch Bailey without any devices, the stack subcell disappeared during layout extraction. Then the precheck said that the hierarchy in the netlist didn't match the hierarchy in the gds (consistency error). We added the resistor to force the existance of the subcell and the error was fixed.
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