@jeffdi @Tim Edwards Ok. I think I'm close to point where I can start debugging the full caravel chip LVS results (magic, netgen*, rule file* are stable. *local versions). I'm using slot-001 from mpw-4 for the layout and the verilog from the full caravel repo pulled from mpw5a of caravel_user_project. I'm noticing a discrepancy in the gpio_default cell counts. Is there an explanation? Are they interchangeable?

Subcircuit summary:
Circuit 1: caravel                                            |Circuit 2: caravel
--------------------------------------------------------------|--------------------------------------------------------------
EP_gpio_defaults_block_0403 (35)                              |gpio_defaults_block_0403 (3) **Mismatch**
EP_gpio_defaults_block (1)                                    |gpio_defaults_block (33) **Mismatch**    
EP_gpio_defaults_block_1803 (2)                               |gpio_defaults_block_1803 (2)

Was there a change between mpw4 and mpw5?

"magic is stable". . . I'd dispute that right now. I seem to have seriously destabilized it in the last handful of commits. It was sort of stable before then. Was there a particular revision you were planning to use?

😆 Using 8.3.270 at the moment. chip_io was close to the results I wanted (pwell in dnwell gets extracted as a port that has only one connection in the parent) and the sram's extracted without power shorts (which is always good). There's still substrate shorts somewhere, I think, but I feel I can work around them at the moment. Maybe well connections always become ports (even internal nets), but most of the time they're already ports, so it doesn't make a difference? I would hope that pwel inside dnwell wouldn't necessarily need a port because there's no way it should connect to anything in an upper hierarchy.