Hi @Stefan Schippers , really wanted some help on debuggin the post layout simu. No idea wats going on. its a simple AND gate , flattened and extracted from magic. The output is getting distorted. When both inputs are 0 , output is coming ~400mV..Where should i start whats going wrong ? The LVS is passing . @Tim Edwards

check pin order of generated cell and the TB pin order

It looks to me like the pin order on the extracted AND gate is different to what you have in your testbench.

x1 VDD GND IN0 IN1 OUT AND_g5D10_W0p840_L0p5_10_7

in the testbench vs

.subckt AND_g5D10_W0p840_L0p5_10_7 IN0 IN1 OUT VDD VSS

in the netlist

oh !!!!