Hello guys, when doing the

make user_project_wrapper

my vccd1 pins wont match to each other when it checks lvs. Is there any simple solution or common mistake I may have made? I have both my vccd1 and my vssd1 declared in my verilog file and vssd1 pins match but the vccd1 pins don't so I'm confused.

@Steven Kiss Can you post your entire log file?

Here is the entire log file.

Well, that didn't help. How about posting your netlists (gate level verilog and extracted)?

Sorry, I am a new to this, I am pretty sure that

ringosc.v

is what you mean by gate level verilog but I don't know where to find my extracted. Would the extracted be produced from

make <proj_name>

or from

make user_proj_wrapper

?

The gate level netlist should be in

verilog/gl/user_project_wrapper.v

Find your extracted spice netlist with

find openlane/user_project_wrapper -name '*spice'

Here they are, thanks for helping me and putting up with my lack of knowledge when it comes to locating files.

Looking at your extracted spice

Xringosc io_out[0] io_in[1] ringosc/vccd1 vssd1 ringosc

This means that

vccd1

of your

ringosc

is not connected to

vccd1

in

user_project_wrapper

. Can you verify this?

@Steven Kiss Are you using MET4/MET5 for

ringosc

Macro Power Routing?, Is this Macro same as available in caravel ?

@Mitch Bailey Yes that is correct, I just don't know what is causing that to happen. @Dinesh A I am new to this process and I am no sure what I am using for Macro Power Routing nor where to find it.

You can cross check power hook-up in <macro>.lef Here is example PIN VGND DIRECTION INPUT ; USE GROUND ; PORT LAYER met5 ; RECT 5.520 41.050 69.460 42.650 ; END PORT LAYER met4 ; RECT 41.040 5.200 42.640 68.240 ; END END VGND PIN VPWR DIRECTION INPUT ; USE POWER ; PORT LAYER met5 ; RECT 5.520 21.050 69.460 22.650 ; END PORT LAYER met5 ; RECT 5.520 61.050 69.460 62.650 ; END PORT LAYER met4 ; RECT 21.040 5.200 22.640 68.240 ; END PORT LAYER met4 ; RECT 61.040 5.200 62.640 68.240 ; END END VPWR

I just checked the file and I am using met4 and met 5 for power routing as well as it being the same as available in caravel.

I feel this issue related to Latest changes in PDN Routing (MPW6 onwards) which does not hook-up Power to MACRO which uses met-5 inside. https://github.com/The-OpenROAD-Project/OpenLane/issues/1157

Thankyou, this looks like the exact problem I am dealing with. I will go through it.