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I am not getting a DRC error either way, but is there any reason not to have the CMOS well tap direc...
# analog-design
w
I am not getting a DRC error either way, but is there any reason not to have the CMOS well tap directly on the edge of the N well?
If the body diode ever conducts would this make the recovery charge worse? Or impact the beta of the parasitic PNP? As its now N+ on p substrate instead of n well on p substrate?
I see that a rule of
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MV Diffusion width < 0.29um (diff/tap.14)
exists though. Which means that the N+tap can directly abut p-substrate or has to be greater than 0.29um away. Is this distance enough to ensure that the doping of the N+ contact does not impact the junction of the n-well and P-substrate?
t
N-well overlap of N-tap < 0.18um (diff/tap.10)
or 
P-tap spacing to N-well < 0.13um (diff/tap.11)
, if you mean the outside edge. Either way, you should be getting a clear DRC error.
w
Sorry, I got confused. I meant diffusion directly abutting tap
which gives a P+/N+ diode for nwell vs a P+/n-well diode
I am changing the layout of my waffle fet to meet the FOM density requirements and realized I can do it either way. I used to have the diffusion directly adjacent to tap.
I would think that the P+ / n-well diode would be less bad in terms of reverse recovery if it ever conducts as its more lightly doped?
I have already verified this geometry through tapeout so perhaps I should not change things too much though...
t
I will take a look---agreed that something is up with the calculation and I have no guesses about it at all until I've investigated. In principle, the density calculation is trivial. You declare a bounding box, count the area of everything inside that box that isn't space, and divide by the total area. Most likely, the changing value is coming from a changing definition of the bounding box. Right now I have MPW-two silicon sitting on my desk, so that has priority over everything else, except for the fact that I'm supposed to prepare a magic demo for the IEEE video call on Friday. So don't expect much action before the weekend.
w
Wrong reply thread I think?
I seem to have found the root cause, which is it gives incorrect values if there are pending DRC errors. So I have a workaround for now.,
So no rush. Also I think I am nearing the end of my density optimizations. Should be ok given the total switch size.
Also, yay for MPW-two silicon! I better work more on my paper on my buck converter so I can still be one of the first people to publish about working SKY130 silicon 😅
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