Hi everyone~ I tried to use foundry sp/dp SRAM cells to build my circuits. But anyone knows why the spice file for sp SRAM(6T) shows 8 transistors?🙂 And for dp SRAM cell it's 10T right? Do we have any 8T cells?

That's a strange spice subcircuit - no ports! This is the dual port cell included in

$PDK_ROOT/sky130A/libs.ref/sky130_sram_macros/spice/sky130_sram_1kbyte_1rw1r_32x256_8.spice

.SUBCKT sky130_fd_bd_sram__openram_dp_cell BL0 BR0 BL1 BR1 WL0 WL1 VDD GND

X0 Q WL1 BL1 GND sky130_fd_pr__special_nfet_latch W=0.21 L=0.15 m=1
X4 Q_bar WL1 BR1 GND sky130_fd_pr__special_nfet_latch W=0.21 L=0.15 m=1

X3 BL0 WL0 Q GND sky130_fd_pr__special_nfet_latch W=0.21 L=0.15 m=1
X7 BR0 WL0 Q_bar GND sky130_fd_pr__special_nfet_latch W=0.21 L=0.15 m=1

* Bitcell Core
X1 GND Q_bar Q GND sky130_fd_pr__special_nfet_latch W=0.21 L=0.15 m=1
X2 GND Q_bar Q GND sky130_fd_pr__special_nfet_latch W=0.21 L=0.15 m=1
X9 Q Q_bar VDD VDD sky130_fd_pr__special_pfet_pass W=0.14 L=0.15 m=1

X5 GND Q Q_bar GND sky130_fd_pr__special_nfet_latch W=0.21 L=0.15 m=1
X6 GND Q Q_bar GND sky130_fd_pr__special_nfet_latch W=0.21 L=0.15 m=1
X8 VDD Q Q_bar VDD sky130_fd_pr__special_pfet_pass W=0.14 L=0.15 m=1

* tap under poly
X10 GND GND BL1 GND sky130_fd_pr__special_nfet_latch w=0.21 l=0.08 m=1
X11 GND GND BR1 GND sky130_fd_pr__special_nfet_latch w=0.21 l=0.08 m=1

* drainOnly PMOS
X12 Q_bar WL1 Q_bar VDD sky130_fd_pr__special_pfet_pass W=0.07 L=0.15 m=1
X13 Q WL0 Q VDD sky130_fd_pr__special_pfet_pass W=0.07 L=0.15 m=1

* drainOnly NMOS
X14 GND GND BL1 GND sky130_fd_pr__special_nfet_latch w=0.21 l=0.08 m=1
X15 GND GND BR1 GND sky130_fd_pr__special_nfet_latch w=0.21 l=0.08 m=1


.ENDS

Combining the parallel mos and ignoring the

tap under poly

and

drain only

dummy devices gives 8T. The layout is actually extracted as

.subckt sky130_fd_bd_sram__openram_dp_cell wl0 wl1 bl0 bl1 br0 br1 a_38_n79# vdd gnd
+ a_400_n79#
X0 gnd gnd bl1 gnd sky130_fd_pr__special_nfet_latch ad=1.0032e+12p pd=1.314e+07u as=5.04e+10p ps=900000u w=210000u l=80000u
X1 a_38_133# wl0 a_38_133# vdd sky130_fd_pr__special_pfet_pass ad=3.5e+10p pd=780000u as=0p ps=0u w=70000u l=150000u
X2 a_16_183# wl1 br1 gnd sky130_fd_pr__special_nfet_latch ad=3.088e+11p pd=4.43e+06u as=5.04e+10p ps=900000u w=210000u l=150000u
X3 gnd gnd a_400_n79# gnd sky130_fd_pr__special_nfet_latch ad=0p pd=0u as=2.52e+10p ps=660000u w=210000u l=80000u
X4 a_16_183# a_38_133# gnd gnd sky130_fd_pr__special_nfet_latch ad=0p pd=0u as=2.768e+11p ps=4e+06u w=210000u l=150000u
X5 a_16_183# wl1 a_16_183# vdd sky130_fd_pr__special_pfet_pass ad=3.5e+10p pd=780000u as=0p ps=0u w=70000u l=150000u
X6 a_38_133# wl1 bl1 gnd sky130_fd_pr__special_nfet_latch ad=3.463e+11p pd=4.93e+06u as=0p ps=0u w=210000u l=150000u
X7 gnd gnd a_38_n79# gnd sky130_fd_pr__special_nfet_latch ad=0p pd=0u as=2.52e+10p ps=660000u w=210000u l=80000u
X8 gnd gnd br1 gnd sky130_fd_pr__special_nfet_latch ad=0p pd=0u as=0p ps=0u w=210000u l=80000u
X9 a_38_133# a_16_183# gnd gnd sky130_fd_pr__special_nfet_latch ad=0p pd=0u as=0p ps=0u w=210000u l=150000u
X10 br0 wl0 a_16_183# gnd sky130_fd_pr__special_nfet_latch ad=0p pd=0u as=1.05e+11p ps=1.84e+06u w=210000u l=150000u
X11 gnd a_38_133# a_16_183# gnd sky130_fd_pr__special_nfet_latch ad=0p pd=0u as=0p ps=0u w=210000u l=150000u
X12 a_38_133# a_16_183# vdd vdd sky130_fd_pr__special_pfet_pass ad=0p pd=0u as=3.64e+10p ps=800000u w=140000u l=150000u
X13 vdd a_38_133# a_16_183# vdd sky130_fd_pr__special_pfet_pass ad=0p pd=0u as=0p ps=0u w=140000u l=150000u
X14 bl0 wl0 a_38_133# gnd sky130_fd_pr__special_nfet_latch ad=0p pd=0u as=1.05e+11p ps=1.84e+06u w=210000u l=150000u
X15 gnd a_16_183# a_38_133# gnd sky130_fd_pr__special_nfet_latch ad=0p pd=0u as=0p ps=0u w=210000u l=150000u
.ends

When tiling the layout, some of the dummy devices overlap with the neighboring cell, which means that more devices will be extracted than actually exist. However, everything works out when the cells are flattened during compare.

I see, Thank you!