https://revcomp.org/wire-capacitance/ '... Device variance will cause a reversible gate to dissipate more than the expected amount, but it will still function correctly. This is a better outcome than variance causing a CMOS gate to become slower than expected, miss the setup time of the next latch, and cause data corruption..." Erik DeBenedictis. @Matt Venn @Kunal @Mike Frank @Olof Kindgren @Tim 'mithro' Ansell @Tim Edwards @razavi