https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9810919 - Digital Fixed-point Low powered Area efficient Function estimation for implantable devices -- When implemented into 130 nm technology via GOOGLE Sky130 PDK and Openlane EDA tools, the ASIC occupies a space of 0.0625 mm2 which represents a 47% reduction when compared to competitors. In addition, its power consumption is reduced to 6.46 mW at 100 MHz fo and just 0.4 µW at 1KHz fo.

i read the paper, thanks. one question though, the authors scales linearly the area of the design in 65 nm: "The ASIC implemented produces a core area of approximately 0.0625 mm2 which when scaled arbitrarily to a 65nm technology: 65 nm 130 nm = 0.03125 mm2 which as can be seen in table 3, is 47.6% less than its nearest competitor [19] which has an operating core area of 0.088 mm2" is it a normal procedure to estimate the area in another technology node by linearly scaling the area of the design in current tech node?