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hi, simulation gets stuck during the power calculation phase while I tried to harden the user projec...
# openlane
b
hi, simulation gets stuck during the power calculation phase while I tried to harden the user project. what could be the reason?
v
set ::env(STA_REPORT_POWER) 0
Update this in config.tcl and try
file a github issue for this
b
I modified the config file of user project. But the problem persists. And the problem is with the project I have created, not the example caravel user project
v
have you defined right 
CLOCK_PORT
?
log shows no launch/capture paths found
b
I used wishbone clock. so I didnt modify clock_port in the config file
cud the reason be usage of more area?
v
without test case its difficult point out reason
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